张峰, 李艳, 陈亮, 李明, 于芳. FPGA结构设计方法及EDA工具[J]. 微电子学与计算机, 2013, 30(5): 14-18,22.
引用本文: 张峰, 李艳, 陈亮, 李明, 于芳. FPGA结构设计方法及EDA工具[J]. 微电子学与计算机, 2013, 30(5): 14-18,22.
ZHANG Feng, LI Yan, CHEN Liang, LI Ming, YU Fang. Methodology and EDA tool for Designing FPGA Architecture[J]. Microelectronics & Computer, 2013, 30(5): 14-18,22.
Citation: ZHANG Feng, LI Yan, CHEN Liang, LI Ming, YU Fang. Methodology and EDA tool for Designing FPGA Architecture[J]. Microelectronics & Computer, 2013, 30(5): 14-18,22.

FPGA结构设计方法及EDA工具

Methodology and EDA tool for Designing FPGA Architecture

  • 摘要: 针对当前FPGA结构设计方法灵活度低、容易出错、自动化程度不够高的现状,提出一种FPGA结构设计方法.根据这种方法实现了EDA工具VA.VA使用GUI编辑结构描述文件,具有使用结构描述文件自动生成FP-GA详细结构的功能,并通过在GUI中局部调整FPGA结构来实现设计异质型布线结构的功能.VA将FPGA结构设计和结构评估功能集成在一起,提供了全自动的评估流程.借助VA,成功设计出一款自主研发的FPGA芯片VS1000,设计过程和结果证明了VA的高效性和正确性.

     

    Abstract: In order to solve FPGA architecture design tools' problems of low flexibility, fallibility, not highly automation, this paper puts forward an FPGA architecture design method and realize this method by an EDA tool VA. VA provides a graphical user interface (GUI) to edit FPGA architecture description file, then converts this high--level architecture description into a detailed and completely specified FPGA architecture. Through VA's GUI, FPGA routing architecture can be readiusted locally, which makes designing a heterogeneous FPGA routing architecture possible. VA integrates FPGA architecture design and evaluation functions together, provides full-- automatic architecture evaluation flow. Finally, an FPGA chip VS1000 is successfully designed by VA, the experiments results of design have proved the correctness and efficiency of VA.

     

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