Abstract: Due to the FPGA necessary to evaluate the reliability of clock domain circuit in safe-critical applications. Metastable parameter τ is a key parameter to influence the clock domain circuit's MTBF value. This paper first put forward a step-down method to measure the FPGA device's metastable parameters τ. Then design the test circuit which use the internal FPGA digital time management module. The experiment result which based on the typical FPGA chip shows that the step-down method can effectively test the FPGA metastable parameterτ and T_w, and is easy and convenient to operation.