Abstract: This paper presents a VLSI architecture of an expression-grained reconfigurable array, which is mainly used for applications with high computation-intensity and data-parallelism, like video decoding.Each processing element contains 4 heterogeneous data-path units and an expression can be mapped on it.There is a three hierarchy levels interconnect structure between PEs.The array contains 128-bit data memories and has the capability of data distributing and joining.The kernel computing loop can be mapped on the array.We developed an architecture prototype with 16 PEs and synthesized it using TSMC 90nm process library.The frequency is about 100MHz and the core area is about 1.38mm2.The algorithm of 2D-DCT is simulated and compared with other architectures, and the result shows that our architecture has better computing and area efficiency.