Abstract: To satisfy the need of hardware implementation for JPEG 2000 encoder,a high-performance architecture is proposed for the Tier-1 encoder that is the most complicated and time-consuming.The proposed architecture introduces pass-parallel bit-plane encoder which is based on stripe-skip algorithm within every pass to raise the coding speed.Meanwhile to work with the bit-plane encoder,the MQ encoder utilizes a dynamic 5-stage pipeline to increase the coding efficiency more.The results of verification realized on FPGA show that the efficiency of Tier-1 encoder is raised 70% with the proposed architecture and it causes 18.2% cost in hardware.Finally,the results are acceptable.