8B/10B编码器新型算法结构的设计与实现
Design and Implementation of New Structure 8B/10B Encoder
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摘要: 针对目前数据传输对高速率的要求, 在保留传统8B/10B编码优点的基础上, 设计并实现了一种8B/10B新型算法结构, 完成数据码和特殊码并行编码, 编码器通过Cadence的NCVerilog进行功能验证, 完成电路仿真与实现.通过Synopsys的Design Compiler工具在SMIC65 nm工艺下进行综合, 该编码器可达到在1 GHz工作频率下占用逻辑资源面积为321 μm2, 具有运行速度快, 占用逻辑资源小的特点.Abstract: In consideration of the demand of high-speed data communication, a new structure high speed 8B/10B encoder is designed and implemented.The proposed encoder architecture is realized based on pipeline and parallel processing.After being synthesized using 65 nm process, the proposed encoder achieves the operating frequency 1 GHz and occupies the chip area of 321 μm2.The results show that it can reduce the area of the circuit and improve the efficiency of encode.
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