Abstract: On the basis of HomePlug AV socket protocol, designed a kind of Channel interleaver/deinterleaver is designed which can apply in the power line carrier communication SOC chip. By setting the top configuration parameters for different files, we can get the half duplex mode working of channel interleaver/deinterleaver in the chip. Through the algorithm and RTL design and ModelSim subsequent Synopsys composite tools DC comprehensive simulation, verify the correctness of the design. The timing results show that at 100 MHz clock, slack(MET) is 2.45, the total cell area: is 22 702.048 020 μm², and the power estimation results are 658.043 4 μW.