一种用于电能计量芯片的高精度低功耗Σ-ΔADC调制器的分析与设计

Analysis and Design of Low Power Σ-ΔADC Modulator Used in Electrical Measurement Chip

摘要: 本文提出了一种低功耗、低温漂的四阶Σ-ΔADC调制器的结构设计, 并在HHGRACE 0.35 μm CZ6H工艺下进行了设计和优化, 经过不同工艺角和温度点下仿真验证, 采样频率为512 kHz, 带隙基准电压的温度系数为25 ppm/℃, 四阶Σ-ΔADC调制器功耗为550 μA左右.芯片流片后在测试电路板上进行了各种功能性能测试, 与仿真结果一致.

Abstract: This paper presents a low power, low temperature drift fourth order Σ-ΔADC modulator design. The proposed low power Σ-ΔADC modulator is designed on HHGRACE 0.35 μm CZ6H technology, and simulated by HSPICE under different process corner and temperature point, system voltage is 5 V, sampling frequency is 512 kHz, the temperature coefficient of bandgap reference voltage is 25 ppm/℃, the power consumption of fourth-order Σ-ΔADC modulator is about 550 μA.The tapeout chip's function and performance is tested on the test board, and the simulation results are consistent.