Abstract: In order to solve the problem of allocating resourcesforFPGA-based convolutional neural network hardware accelerator, a design space exploration method based on fine-grained pipeline architecture is proposed. In order to improve throughput, the method mainly uses three technologies: 1) achieve multi-stage allocation of DSP to balance the pipeline; 2) introduce adjustable intermediate result buffer to coordinate BRAM and DDR bandwidth resources; 3) utilize the depth decomposable convolution to replace part of the convolutional layers to reduce the overall computation of the network. In order to verify the proposed design space exploration method, the YOLO2-tiny network is implemented on the ZC-706 FPGA. Compared with the similar design, the results show thatthethroughput and energy efficiencyofthedesign are relatively higher, and the overall latency is shorter.