Abstract:
Designed a Time Digital Converter (TDC) for the demodulation of GFSK signal.The TDC consists of delay chain,D flip-flop and delay calibration circuit.TDC samples the IF,and converts the frequency information to a binary code.The delay line calibration circuit is used to ensure delay time of the delay cell is accurate.The TDC is designed in 0.18
μm CMOS technology.The layout area is 0.08 mm
2.Simulation results show that the TDC achieves differential nonlinearity of 0.07 LSB,integral nonlinearity of-0.14 LSB and power consumption of 0.9mW,frequency offset tolerance of±350kHz.