田京辉, 黄其煜. 非带隙低功耗低温漂CMOS电压基准电路设计[J]. 微电子学与计算机, 2013, 30(5): 35-37,42.
引用本文: 田京辉, 黄其煜. 非带隙低功耗低温漂CMOS电压基准电路设计[J]. 微电子学与计算机, 2013, 30(5): 35-37,42.
TIAN Jing-hui, HUANG Qi-yu. Design forLow Power Low Temperature Coefficient CMOS Voltage Reference Circuit[J]. Microelectronics & Computer, 2013, 30(5): 35-37,42.
Citation: TIAN Jing-hui, HUANG Qi-yu. Design forLow Power Low Temperature Coefficient CMOS Voltage Reference Circuit[J]. Microelectronics & Computer, 2013, 30(5): 35-37,42.

非带隙低功耗低温漂CMOS电压基准电路设计

Design forLow Power Low Temperature Coefficient CMOS Voltage Reference Circuit

  • 摘要: 通过Vth与VT(热电压)相互补偿原理,提出一种新型非带隙CMOS电压基准源,其输出基准电压具有极低温度系数.采用0.34μm_Foundry18工艺模型和Candance Spectre EDA工具对电路进行模拟验证,获得以下结果:输出电压为552.845mV(T=27℃,VDD=3.3V),温度系数为1.98ppm/℃(-30℃~+130℃),功耗为21.85μw.电源电压从2.5V变到4.5V,输出电压的变化为0.15%(相对于VDD=3.3V时的输出).该电压基准源可望应用于高精度、低功耗IC系统的设计研发.

     

    Abstract: This paper presents a pure CMOS voltage circuit with compensation of VT (thermal voltage) and Vth (threshold voltage). Candance Spectre simulation with 0.34μm_Foundry18 process reports TC (temperature coefficient) is 1.98ppm/℃(-30℃DD) sensitivity of 0. 15% (VDD=2. 5V-4. 5V). The output reference voltage is 552. 845mV (T=27℃,VDD=3.3V). The dissipation is 21.85μw with VDD=3.3V.

     

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