Abstract: This paper proposes a new hardware implementation method for XTS-AES Algorithm that has a full parallel pipelined structure.The proposal scheme increases throughput by unrolling the data path.Meanwhile, it also improves the circuit clock frequency and overall performance by using inner pipelined structure to optimize the critical path.Compared with the currently known highest throughput XTS-AES implementation, the new XTS-AES module increases the throughput by 52.28% in UMC 90 nm CMOS technology.The result indicates that this hardware module fully meets the need of high-speed encrypted storage at present.