Abstract: A method of evaluating electromagnetic information leakage of the CMOS gate circuit was presented by changing the lead in CMOS technology into dipole model.The simulation adopted TSMC0.18 μm process technology, and implemented the NAND gate based single rail logic and SABL double rail logic, meanwhile, the electromagnetic information leakage was evaluated by the given method.The results showed that this method was able to quantitative evaluate the electromagnetic information leakage of the CMOS gate, and that the electromagnetic information leakage of double rail logic gate was much weaker than single logic gate.