Abstract: This paper presents a design of LDPC decoder for the irregular quasi—cyclic LDPC in IEEE802. 1ln standard. Memory minimization scheme in which the size of passing-message memory equals to the number of elements in base matrix is exploited to reduce the memory cost significantly. Offset min-sum algorithm with optimized offset parameters has been used in check node unit of stratified structure． The decoder has been implemented under SMIC 0．13μm CMOS process. The max throughput is 100 Mb／s with power of 73 mW at 1 33．3 MHz frequency.