Abstract:
This paper presents the design and performance of a 3.4~3.6 GHz power amplifier (PA) chip implemented in 2 μm InGaP/GaAs HBT technology.A three-stage cascade configuration is adopted,and the output matching network is designed on the PCB.A series resonant circuit is designed off-chip and connected to the PA chip by a bondwire in order to reduce the 2nd and 3rd harmonics.Under V
cc=4.3 V and V
bias=3.3 V,the measured P
1dB is 28.5 dBm with a PAE of 28.3%,the 2nd and 3rd harmonics are suppressed effectively and the values are -50 dBc and-43 dBc,respectively.Besides,the PA shows good linear gain over 28.3 dB with the gain flatness only ±0.21 dB.