郝明丽, 王统, 陈春青, 张海英. 带有串联谐振支路的3.4~3.6GHz功率放大器[J]. 微电子学与计算机, 2013, 30(8): 142-146.
引用本文: 郝明丽, 王统, 陈春青, 张海英. 带有串联谐振支路的3.4~3.6GHz功率放大器[J]. 微电子学与计算机, 2013, 30(8): 142-146.
HAO Ming-li, WANG Tong, CHEN Chun-qing, ZHANG Hai-ying. A 3.4~3.6 GHz Power Amplifier with a Series Resonant Circuit[J]. Microelectronics & Computer, 2013, 30(8): 142-146.
Citation: HAO Ming-li, WANG Tong, CHEN Chun-qing, ZHANG Hai-ying. A 3.4~3.6 GHz Power Amplifier with a Series Resonant Circuit[J]. Microelectronics & Computer, 2013, 30(8): 142-146.

带有串联谐振支路的3.4~3.6GHz功率放大器

A 3.4~3.6 GHz Power Amplifier with a Series Resonant Circuit

  • 摘要: 基于2μm InGaP/GaAs HBT 工艺技术,提出了一种3.4~3.6 GHz 功率放大器芯片电路的设计.功率放大器采用三级级联放大电路结构,其输出匹配网络设计在片外并通过 PCB 板实现.为了降低二次和三次谐波,在片外输出匹配网络中设计了一种串联谐振支路,并通过一根金丝引线与功放芯片相连.通过上述方法,谐波被有效抑制,在 Vcc=4.3V 和 Vbias=3.3 V 供电下,测得3.4 GHz 下的1 dB 压缩点输出功率为28.5 dBm,相应的功率附加效率为28.3%,其二次和三次谐波抑制比分别达到-50 dBc 和-43 dBc.另外,该功放在整个工作频带上的线性增益超过28.3 dB,增益平坦度达到±0.21 dB.

     

    Abstract: This paper presents the design and performance of a 3.4~3.6 GHz power amplifier (PA) chip implemented in 2 μm InGaP/GaAs HBT technology.A three-stage cascade configuration is adopted,and the output matching network is designed on the PCB.A series resonant circuit is designed off-chip and connected to the PA chip by a bondwire in order to reduce the 2nd and 3rd harmonics.Under Vcc=4.3 V and V bias=3.3 V,the measured P1dB is 28.5 dBm with a PAE of 28.3%,the 2nd and 3rd harmonics are suppressed effectively and the values are -50 dBc and-43 dBc,respectively.Besides,the PA shows good linear gain over 28.3 dB with the gain flatness only ±0.21 dB.

     

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