一种基于EDT的低功耗可测性设计技术研究

A Low Power DFT Technology Based on EDT

摘要: 本文介绍了一种基于ED T的低功耗可测性设计技术，并提出该技术在设置功耗阈值时的优化方案.该低功耗可测性设计技术通过对测试图形进行0填充，使电路在测试过程中的WSA得到有效降低，从31.55%优化到了25.12%.通过设置功耗阈值，降低了测试功耗峰值，实验电路的LST最大值从49.76%优化到21.21%，RST 最大值从45.73%优化到25.00%，并使WSA和SET的最大值得到相应优化.理论研究和实验表明，缩短扫描链长度能够有效提高设置功耗阈值时的测试覆盖率.

Abstract: This paper presents a low power DFT technology based on EDT,and introduces an optimization method when setting power threshold.This low power DFT technology has the ability to reduce WSA during testing by filling 0 to test patterns,which optimizes WSA from 31.55% to 25.12%.Otherwise,setting power threshold can reduce peak testing power,which optimizes LST to 49.76% to 21.21%,RST from 45.73% to 25.00%.Coverage drop,caused by power threshold,could be improved by reducing the scan chains length.