Abstract: Plane clipping and frustum clipping is a key function in GPU 3D engine.But unfortunately, the clipping module is more easy to become the bottleneck of whole 3D engine. This paper proposes a optimized clipping accelerator(CA) architecture, and completes the design and implementation of clipping accelerator. Further, on Xilinx Vertex6 XC6VLX760 FPGA for prototype verification, the frequency of prototype is up to 196 MHz and the functions are correct. In addition, we synthesize the RTL under SMIC 65 nm CMOS library, the frequency of design is up to 315 MHz, which meets the design requirements.