Abstract: Traditional 3DES algorithm requires 48 clock cycles of iterations, which exists the problem of low throughput, while it proposes double-combined-iteration-structure, which costs 25 clock cycles to complete an encryption or decryption calculation, compatible with ECB and CBC operating modes. On Altera's Quartus II 13.0 software for FPGA implementation, the choice of the device EP4SGX530NF45C3, its delay is 3.61 ns, and throughput reaches 709.1 Mb/s, using an area of 650 ALUTs, achieving higher performance compared with similar implementations.