Abstract: Conventional Data-aware structure SRAM has power waste issue in read process due to row half-select, thus this paper proposes an improved 9T SRAM. Compared with traditional SRAM, the proposed scheme solves the power problem caused by the read path of half-selected cells in the selected row. The simulation result proves that the proposed scheme can reduce power dissipation on bitline by 514% at most. A 16kb SRAM test scheme is implemented in 0.13μm technology operating at 0.42V, with with measured power consumption of 5.37μW.