Abstract: Instruction scheduling and reordering are always used to boost instruction parallelism, especially for VLIW DSP processors whose performance is largely exploited by static compilation because of its simple hardware structure. This paper proposes a hyperblock instruction scheduling algorithm considering with register pressure differentiation of intensive and non-intensive code. This algorithm builds the topological order to schedule each node of the data-dependence graph based on priority models. The experimental result shows that the proposed algorithm is effective in exploiting instruction parallelism and improving performance.