Abstract: For developing a block cipher processor with certain flexibility, high performance and power efficiency, a coarse-grained reconfigurable array architecture named BCORE is proposed. Based on the analysis of a set of block cipher algorithms, the necessary processing elements and interconnections are integrated into the array, which can be programmed at runtime by a control mechanism called dynamically partial reconfigurable. AES algorithm is mapped on the reconfigurable array by non pipeline and pipeline style separately. The dynamically partial reconfigurable ability is exploited for pipeline implementation in order to improve performance. Simulation and synthesis result shows that the maximum throughput achieved is nearly 2.5 Gb/s. Comparing with other platforms reveals that coarse-grained reconfigurable array makes a good balance between performance, flexibility and implementation efficiency.