Abstract: In this paper we present a multi-mode decoder architecture for convolutional codes, Turbo codes and block low-density parity-check (LDPC) codes. It can finish viterbi decoding for convolutioan codes, Max-Log-MAP decoding for Turbo codes and Sum-product decoding for LDPC codes, which are based on a novel serial computation unit. It can process Min-Sum as well as Add-Compare-Select (ACS) operations. A configrable coprocessor is realized,and this allows the decoding of a vast number of different channel codes and implementation of various communication standards' channel coding schemes with just one single IPcore. According to 65 nm technology, this results in a Viterbi decoding and LDPC decoding throughput of 300 Mbit/s, and Turbo decoding of 160 Mbit/s, at 600 MHz for an area of 2.1 mm².