韦保林, 熊纯, 徐卫林, 段吉海, 韦雪明. 一种超低功耗无片外电容LDO[J]. 微电子学与计算机, 2015, 32(7): 116-120. DOI: 10.19304/j.cnki.issn1000-7180.2015.07.027
引用本文: 韦保林, 熊纯, 徐卫林, 段吉海, 韦雪明. 一种超低功耗无片外电容LDO[J]. 微电子学与计算机, 2015, 32(7): 116-120. DOI: 10.19304/j.cnki.issn1000-7180.2015.07.027
WEI Bao-lin, XIONG Chun, XU Wei-lin, DUAN Ji-hai, WEI Xue-ming. An Ultra-Low Power Output-Capacitor-Less Low-Dropout Regulator[J]. Microelectronics & Computer, 2015, 32(7): 116-120. DOI: 10.19304/j.cnki.issn1000-7180.2015.07.027
Citation: WEI Bao-lin, XIONG Chun, XU Wei-lin, DUAN Ji-hai, WEI Xue-ming. An Ultra-Low Power Output-Capacitor-Less Low-Dropout Regulator[J]. Microelectronics & Computer, 2015, 32(7): 116-120. DOI: 10.19304/j.cnki.issn1000-7180.2015.07.027

一种超低功耗无片外电容LDO

An Ultra-Low Power Output-Capacitor-Less Low-Dropout Regulator

  • 摘要: 设计了一种超低功耗无片外电容型低压差线性稳压器(OCL-LDO)电路,引入电荷泄放电路和电流倍增缓冲级以改善稳压器的瞬态响应,通过二级密勒补偿技术保证电路在各种负载条件下的稳定性.同时,采用电流模型跨导运放作为误差放大器,有利于简化电路结构和降低功耗.对该OCL-LDO的稳定性及瞬态响应进行了分析并采用SMIC 0.18 μm CMOS工艺设计并流片测试.测试结果表明:在负载电流为1 mA、输入电压为1.9~3.2 V时,输出电压可稳定在1.8 V左右,压差仅为35 mV,且静态电流仅为1.4 μA.

     

    Abstract: An ultra low quiescent current output-capacitor-less CMOS LDO chip is designed in this paper. This Circuit is based on a current-mode transconductance amplifier (CTA) as the error amplifier, and the stability of the circuit under various load conditions is ensured by miller compensation technology. While an instantaneous current-boosting voltage buffer is inserted to improve the transient responses. The stability and transient responses of the LDO regulator are presented, and it has been implemented and fabricated in SMIC 0.18 μm CMOS process. The measured results shown that the output voltage can be stable at 1.8 V when its supply is from 1.9 V to 3.2 V, the dropout voltage is just 35 mV, and the quiescent current is only 1.4 μA.

     

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