基于CCSDS标准的并行帧同步系统的FPGA实现
FPGA Implementation of Parallel Frame Synchronization System Based on CCSDS
-
摘要: 针对空间通信系统中帧同步的数据吞吐率问题,基于CCSDS标准,结合FPGA技术,提出了一种高速并行帧同步方法.首先在Modelsim SE-64 10.2仿真软件上进行了仿真测试,然后通过ISE Design Suite 14.4进行综合、实现,最后在Xilinx的FPGA器件Kintex-7 XC7K325T上进行了板上测试.在Kintex-7 XC7K325T上,该并行帧同步系统的实现可以达到1 Gbit/s以上的数据处理速率.仿真和测试结果表明,该方法采用并行结构以及流水线结构,大大提升了系统的数据吞吐率,同步稳定可靠,并具有帧同步码容错功能.Abstract: An method to perform high speed parallel frame synchronization based on CCSDS standard and FPGA technology is presented for data throughput in space communication.Firstly,logic simulation is made on Modelsim SE-64 10.2.The synthesis and implementation are made according to ISE Design Suite 14.4, and board test is performed in Xilinx Kintex-7 XC7K325T.Its implementation on Xilinx Kintex-7 XC7K325T achieves a data throughput up to 1Gbit/s.The simulation and test results show that with parallel architecture and pipeline architecture,the frame synchronization speed is improved enormously and steadily. The design also takes error margin into account.
下载:
