蔡冰清, 白国强. 基于FPGA的HMAC-SM3硬件实现[J]. 微电子学与计算机, 2015, 32(7): 17-19,24. DOI: 10.19304/j.cnki.issn1000-7180.2015.07.004
引用本文: 蔡冰清, 白国强. 基于FPGA的HMAC-SM3硬件实现[J]. 微电子学与计算机, 2015, 32(7): 17-19,24. DOI: 10.19304/j.cnki.issn1000-7180.2015.07.004
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CAI Bing-qing, BAI Guo-qiang. Implementation of HMAC-SM3 Algorithm on FPGA[J]. Microelectronics & Computer, 2015, 32(7): 17-19,24. DOI: 10.19304/j.cnki.issn1000-7180.2015.07.004
Citation: CAI Bing-qing, BAI Guo-qiang. Implementation of HMAC-SM3 Algorithm on FPGA[J]. Microelectronics & Computer, 2015, 32(7): 17-19,24. DOI: 10.19304/j.cnki.issn1000-7180.2015.07.004
shu

基于FPGA的HMAC-SM3硬件实现

Implementation of HMAC-SM3 Algorithm on FPGA

    摘要
  • 摘要: 首次给出了以SM3作为底层函数的带密钥的消息认证码(HMAC)硬件实现过程.该实现采用了优化过的SM3子模块以及多次复用一个SM3模块,从而达到既节省面积,又在一定程度提高了实现吞吐率的效果.

     

    Abstract: An implementation of the HMAC algorithm with an underlying hash function SM3 is presented. Multiplexed module SM3 and carry-save adder are applied in this implementation to achieve a better performance.

     

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