Abstract: With the integrated circuit feature size decreasing, the sensitivity of CMOS circuits to single event effect is increasing and leads to soft errors. In order to reduce soft error rate of integrated circuits, a soft error tolerant robust latch is proposed. By means of separating the gate of NMOS and PMOS transistors in an inverter to build redundant storage nodes, the latch could be immune to SEU. Taking advantage of filtering pulse design, the latch can mask SET. HSPICE simulation results show that the proposed latch has advantages on fault tolerance performance and overheads comparing with the reference designs, and has less sensitive to process and temperature variation.