A Charge Pump Phase-Locked Loop (CPPLL) circuit is designed based on the 22 nm Fully Depleted Silicon-On-Insulator (FDSOI) process. The circuit makes full use of the back gate bias of FDSOI device to improve the performance of Voltage Controlled Oscillator (VCO). It is composed of a Phase Frequency Detector (PFD), a Charge Pump (CP) and a VCO with low phase noise. The system simulation and phase noise are carried out from the theoretical model, and then the circuit design and circuit noise reduction are carried out based on the theoretical parameters. The simulation results show that the Phase Locked Loop (PLL) has a locking time of 3 μs, the charge pump mismatch current is less than 1%, the phase noise of VCO reaches −100.4 dBc/Hz@1 MHz, and the layout area is 0.14 mm2
. It shows that the circuit has the advantages of fast locking, low phase noise and accurate output frequency.