Abstract: In order to achieve efficient utilization of energy, lowering the power consumption of MOSFET by reducing the on-resistance and gate-drain capacitance of the device has always been a research focus of power electronics, but these two parameters have to trade off. The material advantages of silicon carbide make silicon carbide MOSFET more suitable for high frequency applications. The key point of this paper aims at reducing the gate-drain capacitance to lower the dynamic power consumption in high frequency applications without increasing the on-resistance too much. A silicon carbide trench MOSFET structure with trench source and N-type wrapped region is presented, which is called the Trench Source with N-type(TSN)device. By converting the gate-drain capacitance into the form of gate-source and drain-source capacitance series, the gate-drain capacitance is reduced on the premise that the on-resistance of MOSFET does not increase too much. Then the device structure and manufacturing process of the TSN MOSFET are introduced. The depth of gate groove, the doping concentration and width of N-type wrapped region, the vertical injection depth and horizontal injection depth of P+-type buried layer, and the depth of source groove are optimized by TCAD simulation. The simulation results show that the breakdown voltage of TSN structure is 1420V, the specific on-resistance is 3.121mΩ·cm² and a specific gate-drain capacitance of 12.4pF·cm^-2 is achieved. At approximately the same breakdown voltage of the conventional UMOS structure, although the specific on-resistance of the proposed device increases slightly, the specific gate-drain capacitance decreases significantly. The product of these two parameters is decreased by 78.9%.