Abstract: In this work, an improved LDMOS on SOI substrate is proposed with a varied lateral doping(VLD)drift region in an ultra thin silicon film. By optimizing the fabrication process of the drift region, the surface electric field peak is reduced, leading to an increase of the lateral breakdown voltage. The critical field ratio of SiO2 to Si is improved by forming an ultra thin drift region above the buried oxide, resulting in an enhanced vertical breakdown voltage. After one-time injection, high-temperature diffusion is adopted to form the linear distribution of the drift region, which simplifies the process flow. The injection window of the drift region is optimized to achieve a better linear distribution of the concentration of the drift region. The drift region is thinned by etching and then oxidation, which reduces the process requirements. This paper focuses on the theoretical and Simulation Research of the influence of key process parameters on the breakdown characteristics of devices, analyzes and discusses the key process parameters that affect the breakdown voltage of devices, simulates and analyzes the process flow and characteristic parameters of devices through TCAD software, and obtains the optimized process conditions. Compared with similar high-voltage devices, the device with this process structure has a high breakdown voltage of 1036V, the threshold voltage of the device is 1.3V, and the specific on resistance is 291.9mΩocm2. The thickness of SOI silicon layer used in the device proposed in this paper is 3μm. It is easy to be compatible with vertical NPN and high voltage CMOS devices, which provides a reference for the research of SOI high voltage BCD process integration.