Abstract: In recent years, the research of embedded processor based on RISC-V instruction set has developed rapidly in China. The research on performance evaluation is mostly focused on the small scale and low power processors with 2-3 level pipelined architectures, and there are few studies on the performance quantification of the processors with 5-level pipelined architectures. To solve this problem, based on the traditional five-level sequential pipelining architecture, the strategy of processor optimization is analyzed from the aspects of RISC-V instruction prediction, pipelining mechanism, multiplication and division algorithm, storage architecture, etc. For the processors optimized for different strategies, AHB on-chip interconnection and APB-bridge are used to carry external modules. The software and hardware co-simulation verification is completed on FPGA, and the performance evaluation test program Coremark is run on Xilinx's XC7K325T development board. According to the running results, the influences of different static prediction algorithms, different cycle multiplication and division operations, capacity and design of plug-in storage on the processor are analyzed emphatically. The final processor is based on RV32IMZicsr architecture, and adopts performance optimization strategies such as semi-static prediction (resource optimization), pipeline detection and forwarding mechanism (processing optimization), short-period multiplication-division method (computing optimization), and optimal storage architecture (pointing and memory access optimization). Coremark scored 3.06 Coremark /MHz.