Reliability Calculation for Gate-level Circuit Based on Error Probability Propagation Model

This paper builds a conductor error PTM propagation model, the logic gate of error PTM loading onto the wires are calculated, computed the correct logic gate output probability, finally a layer of door correct output probability is calculated, the probability is the reliability of the entire circuit. This method effectively reduces the time and space complexity, can apply to the reliability evaluation of VLSI circuit by comparing with traditional PTM.