ZHOU Peng-fei, ZONG Zhu-lin, XIAO Long. The Memory Architecture of PON Structure Avionic Bus Protocol Chip[J]. Microelectronics & Computer, 2013, 30(9): 5-8.
Citation: ZHOU Peng-fei, ZONG Zhu-lin, XIAO Long. The Memory Architecture of PON Structure Avionic Bus Protocol Chip[J]. Microelectronics & Computer, 2013, 30(9): 5-8.

The Memory Architecture of PON Structure Avionic Bus Protocol Chip

  • In order to improve the efficiency of the data storage and reduce bus power consumption, a kind of memory architecture with the characteristics of shared storage, circular storage, and global double buffering mechanism has been presented,which is based on the analyses of transmission characteristics of FC -AE bus rely on PON structure.The experimental results show that this architecture has merits of high reliable performance,low delay time and low power dissipation,by testing the co -verification platform with the hardware and software.
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