A Low Power Multiplier with Modified Carry Save Array

The low power and small area of the multiplier is widely in the electrical energy acquisition, A High quality of 16×16 multiplier with Carry Save Array is designed. The modified Booth-4 algorithm is adopted to generate partial product and the design of modified CSA is introduced to compress the partial product, eliminating the propagate adder at the final stage of the conventional multipliers. Due to removal of a few transistors in the array architecture, the proposed multiplier with Carry Save Array reduces the power dissipation and the area. In the design, At the voltage of 2.0 V, the H-spice is used to carry out the results for 0.6μm SMIC technology which reveals the proposed design has a measured power dissipation of 8.98 mW and that multiplication time of multiplier is 8.76ns at a frequency of 150 MHz.