Design and Implementation of a Real Time and High Performance Static Memory Controller IP Compatible with AMBA Bus

A static memory controller IP compatible with AMBA2.0 bus was designed.Compared with virtual memory management, this IP highly enhanced the real-time ability of a real-time system chip since the maximum delay of one access was two clock cycles and the minimum delay was zero.Meanwhile this IP was with a simple structure and supported eight configurable 64 MB banks to control different static memories.A structure-paralleled and timing-synchronous design was adopted.The static memory controller was implemented with SMIC 0.18 μm process and the whole SoC area was 5 mm×3.5 mm.The test results were in good agreement with the design specification.