A polar code decoding algorithm based on pre-judgment mechanism and its VLSI architecture

This paper proposes a pre-judgment mechanism based on log-likelihood ratio, reducing redundant split for SCL (RRS-SCL). According to the log-likelihood ratio symbol decision of each layer, it is split into "1" or "0" and the fixed bit layer are directly split into known bits, which aims to reduce path splitting and remove redundant path metric calculations by directly inheriting the path metrics from the previous layer. Based on the scheme, we design RRS-SCL VLSI architecture with code length N=1024, the code rate R=0.5, and the list width L=2. The experimental results show that the throughput can be achieved at 160Mbps under 384MHz and delay is reduced by approximately 51%.