A Phase Noise Analysis Method for High Frequency LC-VCO

Based on the design requirement of the 25.2 GHz integer charge pump phase-locked loop (CPPLL), a low-phase noise LC voltage-controlled oscillator with a center resonant frequency of 25.2 GHz was designed by using the TSMC90 nm CMOS process. Based on the working principle of single-balanced mixer, the mathematical model of phase noise of tail current source was analyzed and established and reasonably optimized. The simulation and measure results indicated that the LC voltage-controlled oscillator had a resonant frequency range of 22.75~28.5 GHz, whose phase noise was -100 dBc/Hz@1 MHz, and the circuit power consumption was15 mA.