Design and implementation of mixed radix reconfigurable Fast Fourier Transform processor

This paper presents a novel mixed radix reconfigurable FFT processor, which consists of a new reconfigurable butterfly unit supporting radix-2/3 FFT and multi-channel parallel collision-free memory, which implements multi-channel data parallelism and the continuity of the operation for FFT operation. The maximum frequency of this design is 1.06 GHz under the TSMC28nm process. At the same time, the mixed radix FFT processor hardware test system based on the Xilinx's XC7V2000T FPGA chip completes performance verification. The results shows that the design supports FFT operations for radix-2 mode, radix-3 mode and radix-2/3 mixed mode, and the execution speed reaches the theoretical period value under the given number of butterfly multipliers. For single-precision floating-point numbers, mixed radix FFT processor provides a result accuracy of 10^-5.