Analysis and Optimization of High-Efficiency Standard Cells Operating With in Wide-Range Supply Voltage

In this paper, we study the influence of 'Eliminating big fan-in logic gates' method, and finally prove that circuit synthesized with this method behaves little performance deterioration or energy increase, its main effect is increasing circuit area in some cases. We also optimize the structure of D flip-flop with asynchronous set and reset, and voltage up level shifter, which reduces their transition delay for 14.6% and 19.9% when operated at low source voltage, respectively. Thus our work solve the problem which is induced by the performance deterioration of near-threshold operating.