The design and implementation of 10 gigabit ethernet link based on FPGA

Based on the FPGA hardware, this paper designs a 10 Gigabit Ethernet link transmission system. Simplifying the seven-layer OSI model, the paper designs a five-layer network transmission model and deeply studies the transport layer, network layer and data link layer. A complete UDP/IP protocol, ARP protocol and 10 Gigabit data link layer MAC controller are implemented. The UDP/IP protocol implements data encapsulation and decapsulation. The ARP protocol solves the mapping problem between IP address and MAC address, which is conducive to build a large-scale system. Using repeated CRC units, the paper implements CRC with zero delay, which speeds up the data transmission process. The system was designed and implemented on the Xilinx-based Kintex UltraScale device and the system function test was performed on the MC02 development board.