Design of a Fully Pipelined Double-Precision Multiply-Add-Fused Unit

This paper presents a fully pipelined double precision MAF (Multiply Add Fused unit, A×C+B), which accepts denormalized numbers.The unit is based on combination of the rounding with final addition, moreover, a method to deal with the one bit error from the carry saved format of multiply result is proposed, finally, the rounding architecture is improved for getting better pipeline structure.The overall MAF has a latency of 3 cycles a throughput of 1 cycle, and a frequency of 333MHz in 0.13 μm CMOS technology.