Constructral Modeling Method and Simulation for Pipeline ADC Using VHDL-AMS

A large amount of analog-to-digital converters(ADC)lack of simulation model now, a constructral modeling method for pipeline ADC using VHDL Analog and Mixed-Signal Extensions(VHDL-AMS)is proposed in this paper in order to meet the necessary of modeling and simulation of large analog/mixed signal system.Multi-bit/stage 12 bit, 10 MSPS pipeline ADC is taken as modeling object, accroding to its architectural character, the VHDL-AMS sub-model of Sample-Hold Amplifier and Multiplying Digital to Analog Converter is built respectively with taking account of nonideal factors, and then the architectural model of high level pipeline ADC is built by instantiating.By the co-simulation of SystemVision and Simulink, intatic performance parameter Differential NonLinearity(DNL)and Integral Non-Linearity(INL)are all less than 1 LSB; dynamic performance parameter Spurious Free Dynamic Range(SFDR)is 94.9417 dB, Total Harmonic Distortion(THD)is-94.9419 dB, Signal to Noise Ratio(SNR)is 58.7544 dB.The result shows that the proposed modeling method is reasonable and verified.