Design of a Fast-Lock Phase-Locked Loop with Wide Band Width Based on 40 nm CMOS

Through improving the phase frequency discriminator circuit structure,and adding a control module to control charge pump current,a charge pump phase-locked loop circuit which has the characteristics of fast-lock and wide band has been designed.When the phase error value of the phase frequency discriminator is greater than the delay timeτ of the control module,the control switch is opened to increase the charge pump current,the loop bandwidth is increased,at the same time the resistance of the loop filter is reduced,realized fast lock,loop stability do not change.When the loop is close to lock,the bandwidth is adjusted to the presupposed optimization value to get a system of optimal characteristics.Based on SMIC 40 nm CMOS process,a phase-locked loop is designed,contain circuit and layout design.The results of simulation show:The output frequency covered GSM,TD-SCDMA,WCDMA,TD-LTE four communication standards working frequency band,in other words,the output frequency ranges for 698~960 M Hz,1 700~2 200 M Hz,2 300~2 700 M Hz with a setting time of less than 12μs at a 2.5 V supply.