A 14-bit 200 MS/s Current-steering D/A Converter

A 14-bit current-steering digital to analog converter with segmented structure is designed and fabricated by SMIC 0.18 μm technology in this paper. It adopts 5+4+5 segmented architecture and both binary and thermometer decoder are resulted in this design. Cascode current source construction is adopted to improve its output impedance which is crucial to the performance of the proposed DAC. Q² Random Walk switching scheme is applied to ensure the systematic and decrease the graded errors in the layout of current source. With 0.999 3 MHz input signal and 200 MHz sample clock the SFDR of the DAC is over 90 dB.