Implementation of High-speed Parallel Multiplier Based on Optimized Partial Product

An improved architecture of partial product generation and compressing units is researched in this paper.By optimizing the partial product generating algorithm with multiplexers in stead of traditional AND and OR gates, the performance of partial product circuits is improved.Meanwhile, the area and power consumption of the module is also decreased.Optimized compressor units enhance the speed of partial product compression processing.The results of synthesis and verification for 16×16 parallel multiplier show that its performance was increased by 14.5%, as well as the area decreased by 7.1% and the power consumption reduced by 17.2%.