Buffered Clock Tree Routing for 3D-IC

To get a cost-effective implementation of clock trees in 3D-IC designs based on TSV (Through-Silicon Via),a 3D clock tree synthesis algorithm is proposed.For a topology given abstract tree,we introduce a 3D clock tree embedding algorithm to minimize the number of TSVs.If abstract tree is not given,we introduce a nearestneighbor-3D algorithm to generate an abstract clock tree.Finally,buffers are inserted to reduce delay and maximum load capacitance.These steps make the clock tree synthesis algorithm.Through experiment,we confirm that the clock tree synthesis with this algorithm is very effective in terms of total wirelength,delay,power consumption and the number of TSVs.Thus,it relieves the thermal and cost issues of 3D-IC.