Dynamic Reconfigurable Array Processor Design

This paper describes an improved reconfigurable array processor — IRAP (Improved Reconfigurable Array Processor) . In this design computation part of the array processor is divided into four quadrant region, every region contains processing elements. The processing elements in each region could have different configuration during computation, which improves the configuration flexibility and efficiency of the system. Also, the connection of processing elements is optimized according to the butterfly algorithm in image processing. Then the implementation of FFT algorithm on IRAP is introduced. The simulation results show that IRAP achieves higher performance than prototype.