The Design of an Instruction Scheduler in a Simultaneous Multi-threaded Processor

The simultaneous multithreaded processor is for graphics, image and digital signal processing and can be realized instruction-level parallelism(ILP) and thread-level parallelism(TLP) of light-core processors. The design of such a processor simple structure dynamic instruction scheduler is presented here for avoiding structural conflict between the four active threads instruction and some special instruction of the different requirements of scheduling. The results showed that, SMT processor instruction scheduler scheduled for execution by the order of each thread, four threads probability of being selected are close to 25%.