Design of an FFT/IFFT Processor for 802.11ac System

In this paper, an area-efficient 8-channel 128 point MRMDC FFT/IFFT processor is proposed for IEEE 802.11ac standard MIMO-OFDM system.The proposed FFT processor is based on MRMDC architecture and supports 8 spatial data steams. Using input and output data sequential reorder architecture in the proposed FFT processor can realize eight input and output spatial data streams all in natural order, and can be used directly in MIMO-OFDM system.The proposed FFT processor is designed in hardware description language (HDL) and synthesized to gate-level circuit using SMIC 0.18μm CMOS process.We choose 12-bit word width for the internal data path and twiddle factors.The processor can provide a thoughput rate of up to 1 Gb/s and maximal clock rate of 100 MHz.