Design and Implementation of a High-resolution SRAM Timing Parameters Measuring Circuit

A common DTC(Digital-to-Time Converter)circuit structure has been optimized, it is able to achieve twostage adjustment levels, both coarse and specific level.With the SMIC 130 nm technology, the adjustment range of the DTC structure reaches 0 ~ 2.0ns and the resolution achieves 5ps.Meanwhile, the area of circuit is can be cut down by 50%, and non-linear error is optimized as well.Based on the improved DTC, two measuring schemes are designed to measure the setup time and hold time for input ports, and the data access time for output ports.The simulation result shows that the overall measurement error is less than 3.33%.