Design of Pipeline Large Integer Multiplier Based on an Implementation of Radix-4 Modified Booth Encoding

A large integer multiplier is the engine of cryptography chip and determines the performance of cryptography chip.In this paper,we propose a new implementation of radix-4 modified Booth encoding,which has a shorter delay than methods proposed in previous works.Upon this encoding method,we also propose a new structure of 256-bit three stage pipeline multiplier.After synthesizing based on SMIC 0.18 mm CMOS process,the critical path delay of the multiplier is 3.77 ns,which is superior to that of other multipliers.