YANG Zheng, HAN Jun-gang, LIU Huan, LI Mao-liang. Design and Implementation of the Pixel Cache in "Firefly 2nd GPU"[J]. Microelectronics & Computer, 2017, 34(4): 98-101, 105.
Citation:
YANG Zheng, HAN Jun-gang, LIU Huan, LI Mao-liang. Design and Implementation of the Pixel Cache in "Firefly 2nd GPU"[J]. Microelectronics & Computer, 2017, 34(4): 98-101, 105.
YANG Zheng, HAN Jun-gang, LIU Huan, LI Mao-liang. Design and Implementation of the Pixel Cache in "Firefly 2nd GPU"[J]. Microelectronics & Computer, 2017, 34(4): 98-101, 105.
Citation:
YANG Zheng, HAN Jun-gang, LIU Huan, LI Mao-liang. Design and Implementation of the Pixel Cache in "Firefly 2nd GPU"[J]. Microelectronics & Computer, 2017, 34(4): 98-101, 105.
Design and Implementation of the Pixel Cache in "Firefly 2nd GPU"
In order to improve the speed of instructions and data transfer in "firefly 2nd GPU", we designed a pixel cache connect the FOP, 2D graphics accelerator and frame buffers. It uses the LRU algorithm and two ways group connected mapping mode, successfully received from FOP and 2D graphics accelerator sends instructions, datas, and address, as well as send them to Storage Manager (MMU).
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